Digital-Intensive Continuous-Time Delta-Sigma Analog-to-Digital Converter for High-Resolution and Low-Power Sensor Interfaces

Prof. Seung-Tak Ryu’s group at KAIST has developed a digital-intensive continuous-time (CT) delta-sigma modulator (DSM) architecture with successive approximation register (SAR)-assisted digital noise coupling (DNC) that enhances energy efficiency, flexibility, and scalability by shifting much of the analog noise shaping into the digital domain. Traditionally, CT DSMs are highly analog-intensive, relying on static, power-hungry opamps. In contrast, the proposed digital-intensive CT DSM, where most building blocks are realized digitally, achieves world-class performance while substantially reducing power consumption and chip area. These advantages provide strong potential for future high-resolution, energy-efficient analog-to-digital converters (ADCs) optimized for advanced technology scaling as well as sensor applications.

The architecture introduces several key innovations. First, a digital integrator inside the feedback loop mitigates overloading issues in higher-order noise coupling implementations, enabling a wider maximum stable amplitude (MSA). Second, the addition operation of the DNC filter is performed directly in the charge domain using the existing SAR CDAC, thereby eliminating propagation delays previously caused by digital adders. Third, a third-order DNC is implemented to further suppress quantization noise, relying solely on digital delay cells. A major highlight is the first ever demonstration of a fourth-order digital-intensive single-loop CT DSM using only a single analog integrator, with all remaining noise shaping realized digitally. Despite the minimalist design, the prototype fabricated in a 28-nm CMOS process achieves a high MSA of –1.6 dBFS, excellent linearity, and stable SNDR across multiple chips, with only ±0.5 dB variation over ten samples across five process corners and ±10% supply variation, demonstrating exceptional robustness.

“This work demonstrates the highest-order digital-domain noise coupling reported to date, highlighting that digital-intensive ADC approaches are both feasible and highly advantageous for advanced technology nodes,” said Dr. Kent Edrian Lozada, the first author and currently a postdoctoral researcher at KAIST.

This research was published in the IEEE Journal of Solid-State Circuits (JSSC), April 2025 Special Issue, as an invited extended paper following its presentation at the IEEE Symposium on VLSI Technology and Circuits (VLSI Symposium), June 2024, Hawaii, USA. The same work also led to multiple paper invitations, including a recent invited tutorial review at the IEEE Custom Integrated Circuits Conference (CICC), April 2025, Boston, USA, which was also nominated for the Best Invited Paper Award, the sole paper from academia among the nominees (official winner to be announced later). In addition, the first author received the prestigious 2025 KAIST College of Engineering PhD Dissertation Award in recognition of the impact of this research. This work was supported in part by Samsung Electronics Company Ltd., under Grant IO201209-07917-01, and in part by the ITRC Support Program by the MSIT, South Korea, under Grant IITP-2020-0-01847.