TickTockStack: In-Datapath Current Imbalance Elimination Using Clocked Differential Logic in a Voltage Stacked Vector Processor

A research team led by Professor Wanyeong Jung at KAIST has developed TickTockStack, a new architecture-circuit co-optimization framework that eliminates data-dependent current imbalance in voltage-stacked vector processors. The work addresses a key obstacle in practical voltage stacking: supply voltage ripplesaused by mismatched current consumption among stacked domains. By combining a vector-processor architecture with clocked differential logic in the datapath, the proposed design substantially improves power delivery efficiency while preserving performance.

In modern high-performance digital systems, a significant fraction of total energy is lost in the power delivery network (PDN), which also aggravates thermal issues and reliability concerns. Voltage stacking is an attractive solution because it reuses charge across circuit blocks connected in series, thereby reducing current demand from the external supply. In practice, however, its benefits are often limited by supply ripples induced by current imbalance. This imbalance becomes particularly severe in conventional CMOS logic, where switching activity depends strongly on input data and causes time-varying current profiles.

To overcome this limitation, the KAIST team designed TickTockStack around a vector processor, whose synchronized execution across multiple lanes naturally suppresses control-induced current variation. The remaining data-dependent imbalance is removed by implementing the datapath with clocked dual-rail domino logic, which maintains a constant activity factor regardless of operand values. As a result, the processor achieves a highly balanced current profile at the gate level. The design also incorporates a fully differential latch-based register file and symmetric multiplexers so that current symmetry is preserved throughout the storage and datapath blocks. Meanwhile, the control path remains in standard CMOS logic to avoid unnecessary area and power overhead in blocks that are less sensitive to activity variation.

Experimental results demonstrate that TickTockStack reduces stack voltage ripples by 6.2× and lowers PDN loss by 33.5% compared with those characteristics of a conventional CMOS-based voltage-stacked design. These benefits are achieved with a modest 18.4% area overhead and no performance penalty. This work suggests a practical and scalable route toward power-efficient SIMD and vector architectures in advanced technology nodes, where PDN efficiency is becoming increasingly critical.

This research highlights the importance of architecture-circuit co-design for future energy-efficient processors. By directly addressing current imbalance at the logic level rather than relying on heavy external balancing mechanisms, TickTockStack provides a compact and effective strategy for making voltage stacking more viable in real digital systems.

This work was supported by an Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean Government (MSIT) (2022-0-00991, IITP-2025-RS-2023-00256472) and the IC Design Education Center (IDEC).