A 14.4-Gb/s 7.3-pJ/b Universal Vision Transformer OFDM Channel Estimation Processor for B5G/6G Communication Systems

A research team led by Professor Youngjoo Lee at KAIST has developed UniC-Vision, the first silicon-proven Vision Transformer (ViT)-based channel estimation processor for beyond-5G and 6G (B5G/6G) communication systems. Through algorithm-hardware co-optimization, the processor hosts the entire neural network on-chip and performs real-time channel estimation across a broad spectrum from sub-6 GHz to millimeter-wave, achieving 14.4 Gb/s throughput at 7.3 pJ/b in 28-nm CMOS. The work was presented at the 2026 IEEE International Solid-State Circuits Conference (ISSCC), and an extended version has been accepted for publication in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I).

Future B5G/6G systems are expected to deliver hyper-reliable low-latency communication (HRLLC), which requires the entire physical layer to complete its processing within 0.1 ms while spanning sub-6 GHz (FR1), millimeter-wave (FR2), and centimeter-wave (FR3) bands. Under doubly-dispersive channels with large Doppler and delay spreads, conventional estimators such as least squares (LS) and linear minimum mean square error (LMMSE) fail to provide channel state information of sufficient quality. Within the artificial intelligence radio access network (AI-RAN) framework, ViT-based estimators deliver markedly higher accuracy. However, their substantial computational and memory demands incur frequent external memory and processor accesses, making it difficult to meet the 15-µs latency budget allotted to channel estimation.

To bridge this gap, the KAIST team introduced two algorithm-hardware co-optimization techniques. Channel-aware compression (CAC) exploits the physical properties of wireless channels, namely the symmetry of the in-phase and quadrature components and the separability of the time and frequency axes, to reduce the neural network parameters by 86%. This allows the complete model to reside in on-chip SRAM, which in turn enables end-to-end layer fusion with zero external access during estimation. Relaxed self-attention (RSA) replaces the costly max-tree and softmax operations with offline-calibrated pseudo-maximum values and a first-order Taylor approximation. This reduces multi-head attention latency by 83% and eliminates the need for an external processor. In addition, a reconfigurable multi-mode architecture matches the patch-embedding dimension to the target frequency range: a full-patch mode captures the complex multipath profiles of FR1, while a quad-patch mode processes four half patches concurrently for the sparser FR2 and FR3 channels, improving throughput by 5× and energy efficiency by 7× over a naive implementation without duplicating any arithmetic resources.

The prototype, fabricated in 28-nm CMOS, achieves a throughput of up to 14.4 Gb/s and an energy efficiency of 7.3 pJ/b at a 1.0 V supply, with a processing latency of 0.28–0.70 µs per resource block that satisfies the 6G requirements. Compared with state-of-the-art channel estimation silicon, UniC-Vision improves estimation accuracy by more than 18.9 dB in mean squared error and energy efficiency by 5.4×, while maintaining a 5G-compatible pilot overhead of only 4.76%. The processor also adapts to varying channel profiles across urban micro- and macro-scenarios without retraining. Link-level simulations with LDPC and Polar decoders confirm at least a 3.6 dB SNR gain over LS estimation at the same target bit error rate.

This work demonstrates that a transformer-based estimator, once considered too heavy for real-time baseband processing, can be brought into silicon with the latency, energy, and spectrum coverage that B5G/6G HRLLC demands. By resolving the memory and computational bottlenecks at the algorithm-hardware boundary rather than by scaling hardware resources, UniC-Vision provides a reliable and efficient channel estimation processor for future wireless systems and paves the way for the practical deployment of AI-native baseband processing.

This work was supported by National Research Foundation of Korea (NRF) grants funded by the Korean government (MSIT) (No. 2022R1A2C2092521, No. RS-2025-02264052) and by an Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the MSIT (RS-2024-00398449, Network Research Center: Advanced Channel Coding and Channel Estimation Technologies for Wireless Communication Evolution). The chip fabrication and EDA tools were supported by the IC Design Education Center (IDEC), Korea.